Time: Wednesdays, 8:30AM- 11:00AM
Place: Hill Center, room 009 (basement of Hill Center) --- Moved from Hill 116
Instructor: Richard Martin

In this class we will read and discuss both classical and recent papers on computer architecture, supplemented by some material in the textbook "Computer Architecture, A Quantitative Approach" (5th edition), by Hennessy and Patterson. The course is structured as a presentations from results in the papers, mostly given by students, guided by the professor. At the end of the class you should have a broad view of computer architecture. Some basics of computer architecture and computer systems are a prequiste of the class. You should understand how to build standard constructs in assembly language, such as conditionals, loops and function calls. You should also understand the basic architecture of a simple microprocessor.

The class work will consist of:

1. Weekly homeworks and participation (25%): Short answers (as homeworks) on the weekly paper readings, as well as 1-2 presentations in class of your answers.
2. Take Home Midterm: (25%)There will be a take home midterm on basic computer architecture concepts and performance analysis.
3. Group project: (25%)Two written project checkpoints, a final presentation to the class, and a final written report.
4. Position paper: (25%) An initial draft position paper, reviews of other student papers, a revised final paper

Class Participation

Position Paper

Project

1. Building a system and demonstrating it.
2. Measuring an existing design, sub-system or component, in some dimension which could be very broad; examples include execution times, hit rates, power, percentages of dark silicon, etc.
3. Measuring some aspect of the environment related to Computer Architecture; e.g. program behavior or program structure.
4. Replicating prior work described in a paper.

Reading Schedule:

Week	Week	Topics	Readings	Questions	Work
number	Date			(Canvas Tests&Quizzes)	Due
1	Jan. 17	Introduction	See slides	Canvas
2	Jan. 24	Values in Design	Friedman,Pitt, Miller	Canvas	Form Project Groups
3	Jan. 31	Basics and Metrics	Hennessy, Chapter 1,Ousterhout, Gabriel
4	Feb. 7	Early Machines	Burks, Lonegran, Ahmdal		Project Proposals Due Fri. Feb. 9th
5	Feb. 14	Memory Hierarchy	Smith Denning, Jacob	Canvas
6	Feb. 21	RISC	Patterson, Patterson and Ditzel Clark Bhandarkar	Canvas
7	Feb. 28	Single Stream Parallelism	Tomasulo,Smith, Yeager, Smith and Pleszkun		Project Checkpoint 1 due
8	Mar. 6	Branch Prediction	Mcfarling, Jimenez,Seznec	Canvas	Position Paper 1st Draft Due
-	Mar. 13	Synchronization	Rajwar,Hammond,Hammond, Wong, et. al.	Canvas
9	Mar. 20	Parallel Machines	Tullsen,Russel,Fisher	Canvas	Position Paper Reviews Due
10	Mar. 27	No Class		Canvas	No Class -- Spring Break!
11	Apr. 3	Accelerators	Brodtkorb,Jouppi,Putnam	Canvas	Project Checkpoint 2
12	Apr. 10	Energy Management	Paul,Lazar Hashemian	Canvas
13	Apr. 17	Security	Yim,Hill
14	Apr. 24	Presentations			Final Project Presentations

Bibliography:

Values in Design

1. Friedman, B., and Kahn, P. H., Jr. (2003). Human values, ethics, and design. In J. A. Jacko and A. Sears (Eds.), The human-computer interaction handbook, 1177-1201. Mahwah, NJ: Lawrence Erlbaum Associates. [Revised second edition, 2008, pp. 1241-1266.] PDF

2. Guns don’t kill, people kill, Pitt, Joseph C., Values in and/or around technologies, In The moral status of technical artefacts, Dordrecht: Springer Netherlands, 2013
3. Is technology value-neutral? Miller, Boaz, Science, Technology, & Human Value, 2021
4. Cory Knobel and Geoffrey C. Bowker,Computing Ethics Values in Design,Communications of the ACM, vol.54, no. 7, July 2011. HTML

5. Nissenbaum, H. "Will Security Enhance Trust Online, or Supplant It?" Trust and Distrust in Organizations: Dilemmas and Approaches. Roderick M. Kramer & Karen S. Cook, Editors Volume VII in the Russell Sage Foundation Series on Trust. Russell Sage Foundation, New York, 2004. (See the Canvas Site Resources Section)

   System Design

6. Butler W. Lampson, Hints for Computer System Design,July 1983. PDF
7. Richard P. Gabriel, The Rise of Worse is Better, 1989 HTML

Early Machines

8. Preliminary Discussion of the Logical Design of an Electronic Computing Instrument, Burks, Arthur W and Goldstine, Herman H and Neumann, J von, Collected works of John von Neumann, 1963, first printed 1949.
10. "Design of the B5000 System", Lonergan, King, 1961
11. "Architecture of the IBM System/360", Amdahl, Blaauw, Brooks, 1964

Memory Hierarchy

12. Cache memories,Smith, Alan Jay,ACM Computing Surveys (CSUR), 1982
13. Virtual memoryDenning, Peter J, ACM Computing Surveys (CSUR),1970
14. Virtual memory: Issues of implementation,Jacob, Bruce and Mudge, Trevor, IEEE Computer, 1998.

RISC

15. Microprogramming David A. Patterson, Scientific American , Vol. 248, No. 3 (March 1983), pp. 50-57
16. The Case for the Reduced Instruction Set Computer, Patterson, Ditzel, 1980
17. Comments on the Case for the RISC, Clark, Strecker, 1980
18. Performance from architecture: comparing a RISC and CISC with similar hardware organization, Bhandarkar, Clark, 1991
19. Oral History of Dave Ditzel,Computer History Museum, 2015
20. simple RISC-V emulator in plain C,fmash16
21. RISC-V Emulator,IdanHo

22. Single Stream Parallelism

23. An Efficient Algorithm for Exploiting Multiple Arithmetic units, Tomasulo, IBM Journal, January 1967
24. Decoupled Access/Execute Computer Architectures, Smith, ISCA 1982 (ACM TOCS version)
25. The MIPS R10000 Superscalar microprocessor, Yeager, IEEE Micro 16(2), 1996
26. Implementation of Precise Interrupts in Pipelined Processors, Smith, Pleszkun, ISCA, 1985 (IEEE Trans. Computer Journal version)

Branch Prediction

27. Combining Branch Predictors, McFarling, DEC WRL Technical Note TN-36, 1993
28. Dynamic Branch Prediction with Perceptrons, Jimenez, Lin, HPCA 2001
29. A case for (partially) TAgged GEometric history length branch prediction, Seznec, Michaud, Journal of Instruction Level Parallelism (JILP), 2006

Parallel Machines

30. Simultaneous multithreading: Maximizing on-chip parallelism,Tullsen, Dean M., Susan J. Eggers, and Henry M. Levy, Proceedings of the 22nd annual international symposium on Computer architecture. 1995.
31. "The CRAY-1 Computer System", Russel, CACM 1978
32. "Very Long Instruction Word Architectures and the ELI-512", Fisher, ISCA 1983
33. IBMs Single-Processor Supercomputer Efforts, Smotherman, Spicer, CACM, 53(1), 2010
34. "Parallel Operation in the Control Data 6600", Thornton, Proceedings of the Fall Joint Computers Conference, vol 26, pp. 33-40, 1964
35. "A VLIW Architecture for a Trace Scheduling Compiler", Colwell et al., IEEE Trans. Computers, 1988
36. "The Tera Computer System", Alverson et al, ICS 1990
37. "Shared Memory Consistency Models: A Tutorial", Adve, Gharachorloo, DEC WRL TR, 1995
38. "The SGI Origin: a ccNUMA highly scalable server", Laudon, Lenoski, ISCA 1997

Hardware Accelerators

39. Graphics processing unit (GPU) programming strategies and trends in GPU computing,Brodtkorb, André R., Trond R. Hagen, and Martin L. Sætra,Journal of Parallel and Distributed Computing,2013

CUDA C PROGRAMMING GUIDENivdia, PG-02829-001_v5.0, 2012, Chapters 1-3

40. Jouppi, et. al., In-Datacenter Performance Analysis of a Tensor Processing Unit, ArXiv.org, Apr. 2017, PDF
41. Putnam, et. al., A reconfigurable fabric for accelerating large-scale datacenter services, ISCA 2014, PDF
42. Han, Sangjin, Keon Jang, KyoungSoo Park, and Sue Moon, PacketShader: a GPU-accelerated software router, In ACM SIGCOMM Computer Communication Review, 2010. PDF
43. Lim, Kevin, David Meisner, Ali G. Saidi, Parthasarathy Ranganathan, and Thoms F. Wenisch. "Thin servers with smart pipes: designing SoC accelerators for memcached." In ACM SIGARCH Computer Architecture News, vol. 41, no. 3, pp. 36-47. ACM, 2013. PDF

    Synchronization

44. Speculative lock elision: Enabling highly concurrent multithreaded execution,Rajwar, Ravi and Goodman, James R. Proceedings MICRO-34. 2001
45. Performance evaluation of Intel transactional synchronization extensions for high-performance computing,Yoo, Richard M and Hughes, Christopher J and Lai, Konrad and Rajwar, Ravi, Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis, 2013
46. Transactional memory coherence and consistency, Hammond, Lance and Wong, Vicky and Chen, Mike and Carlstrom, Brian D and Davis, John D and Hertzberg, Ben and Prabhu, Manohar K and Wijaya, Honggo and Kozyrakis, Christos and Olukotun, Kunle, ACM SIGARCH Computer Architecture News, 2004
47. RETROSPECTIVE: Transactional Memory Coherence and Consistency, Hammond, Lance and Wong, Vicky and Chen, Mike and Carlstrom, Brian D and Davis, John D and Hertzberg, Ben and Prabhu, Manohar K and Wijaya, Honggo and Kozyrakis, Christos and Olukotun, Kunle,

Measurement

48. Ousterhout, John. Always measure one level deeper. Communications of the ACM 61, no. 7 (2018): 74-83.

Security

49. The Rowhammer Attack Injection Methodology, Yim, 2016 IEEE 35th Symposium on Reliable Distributed Systems (SRDS), Budapest, Hungary 2016
50. Hill, Mark D., Jon Masters, Parthasarathy Ranganathan, Paul Turner, and John L. Hennessy. "On the spectre and meltdown processor security vulnerabilities." IEEE Micro 39, no. 2 (2019): 9-19.
51. Lipp, Moritz, Michael Schwarz, Daniel Gruss, Thomas Prescher, Werner Haas, Stefan Mangard, Paul Kocher, Daniel Genkin, Yuval Yarom, and Mike Hamburg. "Meltdown." arXiv preprint arXiv:1801.01207 (2018).
52. Flipping bits in memory without accessing them: an experimental study of DRAM disturbance errors Yoongu Kim, Ross Daly ,Jeremie Kim, Chris Fallin, et al, ISCA 2014
53. RowHammer: A RetrospectiveOnur Mutlu, Jeremie S. Kim
54. MOESI-prime: preventing coherence-induced hammering in commodity workloads Kevin Loughlin, Stefan Saroiu, Alec Wolman, Yatin A. Manerkar, Baris Kasikci ISCA 22
55. Panky, Crypto Primer: Understanding encryption, public/private key, signatures and certificates, HTML

56. John Mitchell, Cryptography Overview, PDF, PPT